Aria Shahverdi

Cryptography

Side-Channel Attacks

Computer Security

Programming

Aria Shahverdi

Cryptography

Side-Channel Attacks

Computer Security

Programming

Download CV
About Me
Hello! I’m Aria Shahverdi.

I am a Ph.D. candidate in the ECE Department at the University of Maryland, College Park MD and I am also a member of Maryland Cybersecurity Center where I am advised by Professor Dana Dachman-Soled. My studies are about the implementation and analysis of cryptographic schemes.

  • Experience in Post-Quantum Cryptography (Lattice-Based Cryptography and Cryptanalysis of Assumptions such as LWE)
  • Side-Channel Attacks (Cache Attacks, Power Analysis Attack)
** Looking for Research Scientist Position and SWE roles. **
Resume
Education
2015 - Present
University of Maryland
College Park, Maryland

Ph.D. in Electrical and Computer Engineering

2013 - 2015
Worcester Polytechnic Institute
Worcester, Massachusetts

M.S. in Electrical and Computer Engineering

2008 - 2013
Sharif University of Technology

B.S. in Electrical Engineering

Experience
May - August 2018
Research Intern
Envieta

Implemented Picnic post-quantum signature scheme using VHDL.

May - August 2015
Design for Security Intern
Mentor Graphics

Measured performance of PUF on FPGA and designed scalable implementation of SIMON.

August 2013 - Present
Research and Teaching Assistant
UMD & WPI
  • For RA responsibilities refer to publications section.
  • UMD: TA for the courses “Computer Systems Security”, “Introduction to Cryptology”.
  • WPI: TA for the courses “Intro to Cryptography” and “Computer Organization and Design”.
Skills
Knowledge
  • Cryptography & Data Security
  • Computer Security
  • Blockchain & Cryptocurrency Technologies
  • Quantum Information Processing
  • Statistical Pattern Recognition (Machine Learning)
Coding
  • Python
  • C / C++
  • Verilog / VHDL
Publication

The order of authors in publications marked with (*) is alphabetical.

If you have any issues accessing the following publications, let me know!

  • (*) D. Dachman-Soled, H. Gong, H. Kippen, A. Shahverdi, BKW Meets Fourier: New Algorithms for LPN with Sparse Parities, TCC 2021.
  • A. Shahverdi, M. Shirinov, D. Dachman-Soled, Database Reconstruction from Noisy Volumes: A Cache Side-Channel Attack on SQLite, 30th USENIX Security Symposium (USENIX Security 21).
  • (*) D. Dachman-Soled, H. Gong, M. Kulkarni, A. Shahverdi, In-Security of Ring LWE Under Partial Key Exposure, Journal of Mathematical Cryptology 2020.
  • (*) D. Dachman-Soled, H. Gong, M. Kulkarni, A. Shahverdi, Towards a Ring Analogue of the Leftover Hash Lemma, Journal of Mathematical Cryptology 2020.
  • M. Chen, A. Shahverdi, S. Anderson, S. Y. Park, J. Zhang, D. Dachman-Soled, K. Lauter, M. Wu, Transparency Tools for Fairness in AI (Luskin), Research in Mathematics and Public Policy 2020.
  • (*) D. Dachman-Soled, M. Kulkarni, A. Shahverdi, Tight upper and lower bounds for leakage-resilient, locally decodable and updatable non-malleable codes, Information and Computation 2019.
  • (*) D. Dachman-Soled, M. Kulkarni, A. Shahverdi, Local Non-Malleable Codes in the Bounded Retrieval Model, PKC 2018.
  • (*) D. Dachman-Soled, M. Kulkarni, A. Shahverdi, Tight Upper and Lower Bounds for Leakage-Resilient, Locally Decodable and Updatable Non-Malleable Codes, PKC 2017.
  • A. Shahverdi, M. Taha, T. Eisenbarth, Lightweight Side Channel Resistance: Threshold Implementations of SIMON, IEEE Transactions on Computers 2016.
  • A. Shahverdi, M. Taha, T. Eisenbarth, Silent SIMON: A Threshold Implementation under 100 Slices, 2015 IEEE Int. Symp. on Hardware-Oriented Security and Trust (HOST).
  • C. Chen, T. Eisenbarth, A. Shahverdi, X. Ye, Balanced Encoding to Mitigate Power Analysis: A Case Study, Smart Card Research and Advanced Application Conference — CARDIS 2014.
  • Y. Doroz, A. Shahverdi, T. Eisenbarth, B. Sunar, Toward practical homomorphic evaluation of block ciphers using PRINCE, Workshop on Applied Homomorphic Cryptography and Encrypted Computing — WHAC’14, 2014.
  • A. Shahverdi, C. Chen, T. Eisenbarth, AVRprince – An Efficient Implementation of PRINCE for 8-bit Microprocessors, Technical Report, Worcester Polytechnic Institute, 2014.
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